Gallery

Background

Aside from my (primary) research activities at EE, IISc, I was also involved in several developmental efforts in parallel---spanning unit-level hardware designs to architecting infrastructural projects in the department. These initiatives chiefly targeted experimental testing & validation of engineering ideas as well as facilitating research at large. I provide a brief summary of these efforts below along with some assorted simulation and experimental results derived over the course of my overall stint (M.E + Ph.D + R.A) at IISc.

Few candid pics that I clicked fondly with certain important figures (& friends) in my professional life are available in:

Candid Clicks



Miscellaneous stuff that piqued my interest are furnished in:

Miscellaneous