Background

On this page, I provide a brief summary of the in-house hardware design and developmental works that I have architected in the past, as a lead or carried out as a collaborative/mentoring effort.

20 kWp Rooftop PV Array

I and Prof. Vinod John spearheaded the installation and commissioning of the 20 kWp rooftop PV array infrastructure (see fig. (a,b)). I architected the rooftop layout architecture, sizing of the PV cables as well as routing scheme to the respective laboratories. The installation was done in collaboration with Madowatt technologies, a private firm that supplied the monocrystalline PV panels (300W each) and handled the civil work. After installation, I carried out common-mode and differential-mode impedance characterization of PV panels with the aid of a network analyzer at various operating points (see fig (c)). This exercise facilitated subsequent development of dynamic models for solar PV-fed PWM converters [see here] as well as the design of improved common-mode filter for grid-tied PV inverters that minimized ground leakage currents [see here].

Location: EE, IISc

Reconfigurable PV distribution box

I architected the above-shown wall-mounted solar PV distribution box (PVDB), serving the twin purpose of--- (a) protection, and (b) allowing flexible (re)configuration of the rooftop PV panels from a location inside the laboratory, to form the larger PV array that suits the given research requirements. The panel cables from the rooftop are brought into the PVDB that is equipped with protection devices such as fuses, MOVs, and DC switches (located on the left side), routed suitably via bus bars and terminated on MC4 connectors with power diodes for bypass and back-feed protection (located on the right side). Five PV outlets (along with DC breaker protection and metering) are provided and run to different Power Electronics labs in the department. The DB outlet protection and cables are designed to handle up to 1000V, 100A. Manufacturing and assembly were handled by Madowatt technologies. Circuit schematics and user instructions are furnished as posters on the panel doors. The DB enables the student to (re)configure the PV panels as per his/her research needs. Location: EE, IISc

20kW General-purpose Inverter Stack (GPIS) Platform

This is a 20 kW 2-level three-phase 4-leg high-performance inverter platform, also known as the general-purpose inverter stack (GPIS) that I designed and developed in-house in 2016 as a graduate student, in collaboration with another (then) fellow grad student, now Dr. Anil Adapa [see here, and here]. The GPIS is based on a PCB-based design (with 4-layer power PCB stack up with tight circuit layout) that uses state-of-the-art (as on 2016) discrete Si IGBTs (200ns transition times), forced-air cooling with BLDC fan, and in-house designed optoisolated gate-drivers for individual switches and protection cards. This design is generic and versatile, in that it can be used as: (a) three-phase DC-AC inverters for grid-tied inverter or motor drive applications, or (b) single-phase back-to-back connected double-conversion system, or (c) interleaved DC-DC converter.  This effort phased out the bulky (and much older) 10 kW IGBT module-based inverter design that was prevalent in the power electronics group until then. The GPIS has served the power group as an enabling platform and has received wide recognition; it has been facilitating research works of several grad students in the power group (at EE, IISc) since 2017, by aiding them in the implementation, verification, and validation of their respective research efforts. This design is also being utilized by researchers outside IISc, including IIT-Bombay, IIEST-Shibpur, NIT-Goa, and other colleges in India.

Ultracapacitor (UC) Stack: 4kW-min capacity

During my tenure as a Senior Research Associate, I drove the effort to model, build and operate a 4kWmin Ultracapacitor (UC ) stack for an AC-microgrid project. In this effort, I mentored a committed and motivated graduate researcher, Ms.P. Roja. The UC stack consists of multiple UC strings housed in a movable metallic rack equipped with DC protection circuits (fuses and breaker), cooling fans, metering devices, and, a switch array for flexible reconfiguration of strings (in series or parallel) as dictated by the research need. The stack consists of four UC strings (see side view ), constructed from series-connected UC cells from Maxwell. The effort of characterizing the UC stack enabled us to uncover several interesting facets of UC behavior, such as its optimal discharge ratio & unstable operating modes [see here], and its inherent nonlinear characteristics [see here]. (UC cells were purchased by another (then) grad student, now Dr. Saichand K.) 

Location: EE, IISc

General-purpose Device Characterization Setup

Islanding Test Setup with Passive RLC load bank