Hardware Developments

Background

On this page, I provide a brief summary of the in-house hardware design and developmental works that I have architected as a lead or carried out as a collaborative (or mentoring) effort at EE, IISc.

20 kWp Rooftop PV Array

(a) PV array

(b) PV panel

(c) Impedance measurement

I and Prof. Vinod John spearheaded the installation and commissioning of the 20 kWp rooftop PV array infrastructure at the Dept. of EE, IISc, Bangalore (see fig. (a,b)). I architected the rooftop layout architecture, sizing of the PV cables as well as routing scheme to the respective laboratories. The installation was done in collaboration with Madowatt technologies, a private firm that supplied the monocrystalline PV panels (300W each) and handled the civil work. After installation, I carried out common-mode and differential-mode impedance characterization of PV panels with the aid of a network analyzer at various operating points (see fig (c)). This exercise facilitated subsequent development of dynamic models for solar PV-fed PWM converters [see here] as well as the design of improved common-mode filter for grid-tied PV inverters that minimized ground leakage currents [see here].

Reconfigurable PV distribution box

I architected the above-shown wall-mounted solar PV distribution box (PVDB), serving the twin purpose of--- (a) protection, and (b) allowing flexible (re)configuration of the rooftop PV panels from a location inside the laboratory, to form the larger PV array that suits the given research requirements. The panel cables from the rooftop are brought into the PVDB that is equipped with protection devices such as fuses, MOVs, and DC switches (located on the left side), routed suitably via bus bars and terminated on MC4 connectors with power diodes for bypass and back-feed protection (located on the right side). Five PV outlets are provided (along with DC breaker protection and metering) that run to different Power Electronics labs in the department. The DB outlet protection and cables are designed to handle up to 1000V, 100A. Manufacturing and assembly were handled by Madowatt technologies. Circuit schematics and user instructions are furnished as posters on the panel doors. The DB enables the student to (re)configure the PV panels as per his/her research needs.

20kW General-purpose Inverter Stack (GPIS) Platform

4-layer Power PCB card

Discrete IGBTs with individual gate drive cards

Fully assembled GPIS

This is a 20 kW 2-level three-phase 4-leg high-performance inverter platform, also known as the general-purpose inverter stack (GPIS) that I designed and developed in-house in 2016 as a graduate student, in collaboration with another (then) fellow grad student, now Dr. Anil Adapa [see here, and here]. The GPIS is based on a PCB-based design (with 4-layer power PCB stack up with tight circuit layout) that uses state-of-the-art (as on 2016) discrete Si IGBTs (200ns transition times), forced-air cooling with BLDC fan, and in-house designed optoisolated gate-drivers for individual switches and protection cards. This design is generic and versatile, in that it can be used as: (a) three-phase DC-AC inverters for grid-tied inverter or motor drive applications, or (b) single-phase back-to-back connected double-conversion system, or (c) interleaved DC-DC converter. This effort phased out the bulky (and much older) 10 kW IGBT module-based inverter design that was prevalent in the power electronics group until then. The GPIS has served the power group as an enabling platform and has received wide recognition; it has been facilitating research works of several grad students in the power group (at EE, IISc) since 2017, by aiding them in the implementation, verification, and validation of their respective research efforts. This design is also being utilized by researchers outside IISc, including IIT-Bombay, IIEST-Shibpur, NIT-Goa, and other colleges in India.

Ultracapacitor (UC) Stack: 4kW-min capacity

Isometric view of the overall stack

Front View

Side View

Single UC string: 1kW-min capacity

As a Senior Research Associate at EE, IISc, I drove the effort to model, build and operate a 4kWmin Ultracapacitor (UC ) stack for an AC-microgrid project. In this effort, I mentored a motivated graduate researcher, Ms. P Roja. The UC stack consists of multiple UC strings housed in a movable metallic rack equipped with DC protection circuits (fuses and breaker), cooling fans, metering devices, and, a switch array for flexible reconfiguration of strings (in series or parallel) as dictated by the research need. The stack consists of four UC strings (see side view ), constructed from series-connected UC cells from Maxwell. The effort of characterizing the UC stack enabled us to uncover several interesting facets of UC behavior, such as its optimal discharge ratio & unstable operating modes [see here], and its inherent nonlinear characteristics [see here]. (UC cells were purchased by another (then) grad student, now Dr. Saichand K.)

General-purpose Device Characterization Setup

GPDCS Assembly

Device failure in SC test

I designed and developed a general-purpose device characterization setup (GPDCS) for switching characterization of semiconductor devices (of TO-247 package) via double-pulse tests at room- and elevated- temperatures. The GPDCS consists of DC capacitors, a half-bridge leg on the PCB (layout mirroring that of the GPIS), gate drivers, and a heat spreader (HS) for the devices along with heating resistors mounted at the top. This architecture enables the setting of desired operating HS (and hence junction) temperatures for the characterization exercise. The setup facilitates comparative study of: (a) thermal interface material and (b) nominal switching and short-circuit (SC) behavior of identically-rated Si and SiC devices from different manufacturers as well as capturing their respective deviations at elevated operating temperatures [see here]. I mentored Ms. P Roja and Ms. Sridevi K (the then Project Assistant), to experimentally validate this effort.


Islanding Test Setup with Passive RLC load bank

Shown on the left here, is the laboratory prototype of an islanding test setup that I developed as a part of my Ph. D. research for studying unintentional islanding behavior of GFL inverters. The setup, in accordance with the IEEE 1547-2014a standard, is composed of a passive RLC load bank and is rated for 230V. It consists of a fixed 5kVAR indictive-load bank and switchable Resistive- and Capacitive-load banks of 5kW and 5kVA, respectively (with a load-step size of 500W and 500VAR). The L and C banks were handbuilt in the laboratory workshop while the R bank was built by an external rheostat vendor (following the given design specifications). The quality-factor (q.f) and resonance frequency of the load bank are nominally set to be unity and 50Hz (grid frequency), respectively, but can be tuned to other values as per the test requirement by suitably setting the R and C values. The setup enables the realization of unintentional grid disconnection scenarios and experimental evaluation passive- and active-anti-islanding algorithms.